module juzhenanjian (shumaout,weiout,swhang,swlie,clk);

output [7:0] shumaout,weiout;

input [3:0] swlie;

output [3:0] swhang;

input clk;

reg [7:0] shumaout,weiout;

reg [3:0] a,key_swhang,key_swlie ,swhang;

reg [32:0] cnt;

reg [32:0] cnt1;

reg [4:0] state,sta;

reg clk1khz;

initial state="d0;

always @(posedge clk)

begin

cnt=cnt+1;

if(cnt<50) clk1khz=0;

else if(cnt<100) clk1khz=1;

else cnt=0;

end

always @(posedge clk1khz)

begin

case(state)

"d0: //判斷是否按下鍵

begin swhang=4"b0000;a="b0;

if(swlie!=4"b1111) begin sta="d1;swhang=4"b1110;state="d5;end //行掃描第一行,第一行為0，判斷列是否是1111是跳到第二行，

else state="d0;

end

"d1:

begin

if(swlie!=4"b1111) state