設計含有非同步清零和計數使能的16位二進位制減法計數器？

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1 # 好嗨嗨的我

解：設clr為非同步清零端，en為計數使能端LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all;USE ieee.std_logic_arith.all;ENTITY ex6_9 IS port( clk : IN STD_LOGIC; clr,en : in std_logic; cnt : OUT std_logic_vector(15 downto 0) );END ;ARCHITECTURE hdlarch OF ex6_9 IS signal cnttmp : std_logic_vector(15 downto 0);BEGINprocess(clk,clr) begin if clr = "1" then cnttmp <= (others => "0");elsif(rising_edge(clk)) then if en = "1" then cnttmp <= cnttmp + 1; end if;end if;end process;cnt <= cnttmp;END;

2 # pietr49411

解：設clr為非同步清零端，en為計數使能端LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all;USE ieee.std_logic_arith.all;ENTITY ex6_9 IS port( clk : IN STD_LOGIC; clr,en : in std_logic; cnt : OUT std_logic_vector(15 downto 0) );END ;ARCHITECTURE hdlarch OF ex6_9 IS signal cnttmp : std_logic_vector(15 downto 0);BEGINprocess(clk,clr) begin if clr = "1" then cnttmp "0");elsif(rising_edge(clk)) then if en = "1" then cnttmp