module d(rst1,rst0,clk,in,out); input rst1,rst0,clk,in; output out; reg out; always@(posedge clk or negedge rst1 or negedge rst0) begin if(~rst1) out<=1; //注意下降沿配套的條件寫法 else if(~rst0) out<=0; //注意下降沿配套的條件寫法 else out <= in; //直接完成D觸發器的特性方程就可以了 //begin //if(in) out<=in; //else out<=out; //end end endmodule

module d(rst1,rst0,clk,in,out);

input rst1,rst0,clk,in;

output out;

reg out;

always@(posedge clk or negedge rst1 or negedge rst0)

begin

if() out //注意下降沿配套的條件寫法

else if() out//注意下降沿配套的條件寫法

else

//begin

//if(in) out

//else out

//end

end

endmodule