這樣不行的，這樣不能奇數分頻。（奇數分頻是要先倍頻再分頻的，比如3分頻的話是要先2倍頻再6分頻。那樣的話，新的時鐘的脈衝沿不是在原時鐘的觸發沿處，而是在電平中變化的。）再說，你前面的IF語句也有錯誤，是產生歧義了。

下面我給你個任意分頻程式吧！

VHDL的任意整數且佔空比為50%分頻程式碼

說明如下：

1.其中topfile為division，其中的clk_com是比較的頻率，用它來和分頻後波形進行比較，便於觀察，

2.any_enve為任意偶數分頻檔案

3.any_odd為任意奇數分頻檔案

4.是一個用於2進位制與8進位制的譯碼器，我用它來顯示在數碼管上當前到底是多少分頻

------thetopfileofthedesigndivision

libraryieee;

useieee.std_logic_1164.all;

useieee.std_logic_arith.all;

useieee.std_logic_unsigned.all;

entitydivisionis

port(input:instd_logic_vector(7downto0);

clk:instd_logic;

clk_out:outstd_logic;

clk_com:outstd_logic;

led1:outstd_logic_vector(6downto0);

led2:outstd_logic_vector(6downto0);

led3:outstd_logic_vector(6downto0));

endentitydivision;

--------------------------------------------------

architecturefreqofdivisionis

componentdecoderis----decoder

port(bin:instd_logic_vector(2downto0);

de:outstd_logic_vector(6downto0));

endcomponent;

componentany_evenis----any_evendivision

generic(data_width:integer:=8);

port(input1:instd_logic_vector(data_width-1downto0);

clk_in:instd_logic;

clk_out:outstd_logic);

endcomponentany_even;

componentany_oddis-----any_evendivision

generic(data_width:integer:=8);

port(input2:instd_logic_vector(data_width-1downto0);

clk_in:instd_logic;

clk_out:outstd_logic);

endcomponentany_odd;

signaltemp1,temp2:std_logic;

begin

u1:decoderportmap(bin=>input(2)&input(1)&input(0),de=>led1);

u2:decoderportmap(bin=>input(5)&input(4)&input(3),de=>led2);

u3:decoderportmap(bin=>"0"&input(7)&input(6),de=>led3);

u4:any_evenportmap(input,clk,temp1);

U5:any_oddportmap(input,clk,temp2);

process(clk,input)

begin

ifinput(0)="0"then

clk_out

elseclk_out

endif;

endprocess;

clk_com

endarchitecturefreq;

libraryieee;

useieee.std_logic_1164.all;

useieee.std_logic_arith.all;

useieee.std_logic_unsigned.all;

entityany_evenis

generic(data_width:integer:=8);

port(input1:instd_logic_vector(data_width-1downto0);

clk_in:instd_logic;

clk_out:outstd_logic);

endentityany_even;

architecturediv1ofany_evenis

signalclk_outQ:std_logic;

signalcoutQ:std_logic_vector(data_width-1downto0);

begin

-------------------------------------------------

process(clk_in)

begin

ifclk_in"eventandclk_in="1"then

ifcoutQ

coutQ

elsecoutQ"0");

endif;

endif;

endprocess;

---------------------------------------------------

process(coutQ)

begin

ifcoutQ

clk_outQ

elseclk_outQ

endif;

endprocess;

clk_out

endarchitecturediv1;

libraryieee;

useieee.std_logic_1164.all;

useieee.std_logic_unsigned.all;

useieee.std_logic_arith.all;

entityany_oddis

generic(data_width:integer:=8);

port(input2:instd_logic_vector(data_width-1downto0);

clk_in:instd_logic;

clk_out:outstd_logic);

endentityany_odd;

architecturediv2ofany_oddis

signalcout1,cout2:std_logic_vector(data_width-1downto0);

signalclk1,clk2:std_logic;

begin

process(clk_in)------risingedge

begin

ifclk_in"eventandclk_in="1"then

ifcout1

cout1

elsecout1"0");

endif;

ifcout1

clk1

elseclk1

endif;

endif;

endprocess;

---------------------------

process(clk_in)------fallingedge

begin

ifclk_in"eventandclk_in="0"then

ifcout2

cout2

elsecout2"0");

endif;

ifcout2

clk2

elseclk2

endif;

endif;

endprocess;

clk_out

endarchitecturediv2;

libraryieee;

useieee.std_logic_1164.all;

entitydecoderis

port(bin:instd_logic_vector(2downto0);

de:outstd_logic_vector(6downto0));

endentity;

----------------------------------------------------

architecturedecoofdecoderis

begin

process(bin)

begin

casebinis

when"000"=>de

when"001"=>de

when"010"=>de

when"011"=>de

when"100"=>de

when"101"=>de

when"110"=>de

whenothers=>de

endcase;

endprocess;

endarchitecture;