library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cnt is

PORT (

rst:in std_logic;

clk: in std_logic;

d:out integer range 0 to 9

);

end cnt;

architecture ONE of cnt is

SIGNAL q:integer range 0 to 9:=0;

begin

process (rst,clk)

BEGIN

if rst="0" then

q

elsif clk"event and clk="1" then

if q=9 then

q

else

q

end if;

end if;

end process ;

d

end cnt;