Verilog實現的4位序列進位加法器（例化了四個一位的全加器）//檔名：add_4.v//模組名：add_4//包含檔案add_full.v//module add_4 ( input [3:0]a, input [3:0]b, input ci, output [3:0] s, output co );wire [3:0] c_tmp;assign co = c_tmp[3];add_fulli0 ( a[0], b[0], ci, s[0], c_tmp[0]);add_fulli1 ( a[1], b[1], c_tmp[0], s[1], c_tmp[1] )add_fulli2 ( a[2], b[2], c_tmp[1], s[2], c_tmp[2] )add_fulli3 ( a[3], b[3], c_tmp[2], s[3], c_tmp[3] )endmodule//檔名：add_full.v//模組名：add_full//module add_full(input a, input b, input ci, output s, output co);assign s = a^b^ci, co=(a&b) | ( ( a|b )& ci );endmodule