LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;ENTITY select1_8 IS PORT(Q:IN STD_LOGIC_VECTOR(3 DOWNTO 0); sel: IN STD_LOGIC_VECTOR(2 DOWNTO 0); D0,D1,D2,D3,D4,D5,D6,D7:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END select1_8;ARCHITECTURE abc OF select1_8 IS BEGIN PROCESS(sel) BEGIN CASE sel IS WHEN "000"=> D0<=Q; WHEN "001"=> D1<=Q; WHEN "010" => D2<=Q; WHEN "011"=> D3<=Q; WHEN "100"=> D4<=Q; WHEN "101" => D5<=Q; WHEN "110"=> D6<=Q; WHEN OTHERS=> D7<=Q; END CASE; END PROCESS;END abc;