library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity cnt16 is

port(clk,r,s,en:in std_logic;

d:in std_logic_vector(3 downto 0);

co:out std_logic;

q:buffer std_logic_vector(3 downto 0));

end cnt16;

architecture one of cnt16 is

begin

process(clk,r,s)

begin

if r="1" then

q

elsif clk"event and clk="1" then

if s="1" then --錯誤的

q

end if;

end if;

if clk"event and clk="1" then

if en="1" and s="0" and r="0" then ----錯誤的

q

end if;

end if;

if r="0" and s="0" and en="0" then

q

end if;

end process;

co

end one;