entity mux4_1 isport ( a,b,c,d: in std_logic; --4位輸入訊號，資料型別自己改s1,s2: in std_logic; --選擇訊號y : out std_logic ); --輸出訊號，資料型別和輸入應一致end entity;architecture bhv of mux4_1 issignal s :std_logic_vector(1 downto 0);begins

entity mux4_1 isport ( a,b,c,d: in std_logic; --4位輸入訊號，資料型別自己改s1,s2: in std_logic; --選擇訊號y : out std_logic ); --輸出訊號，資料型別和輸入應一致end entity;architecture bhv of mux4_1 issignal s :std_logic_vector(1 downto 0);begins<=s1&s2;process(s,a,b,c,d)beginif s="00" then y<=a;elsif s="01" then y<=b;elsif s="10" then y<=c;else y<=d;end if;end process;end bhv;