timescale 1ns/100ps

module testbench;

localparam DATA_WIDTH = 32;

localparam CLK_100_PERIOD = 5;

localparam CLK_200_PERIOD = 2.5;

localparam SIM_TIME = 150000;

localparam ;

localparam ;

reg clk_100, clk_200;

wire clk;

assign clk = clk_100;

always

begin

clk_100 = 0;

forever #CLK_100_PERIOD clk_100 = ~clk_100;

end

always

begin

clk_200 = 0;

forever #CLK_200_PERIOD clk_200 = ~clk_200;

end

reg rstn;

integer fp_testin;

integer fp_matlab_out;

integer fp_sim_out;

integer fp_outdiff;

reg signed [DATA_WIDTH/2-1:0] matlab_in_re, matlab_in_im;

reg signed [DATA_WIDTH/2-1:0] matlab_out_re, matlab_out_im;

reg signed [DATA_WIDTH/2-1:0] matlab_diff_re, matlab_diff_im;

reg signed [DATA_WIDTH/2-1:0] matlab_diff_re2, matlab_diff_im2;

reg signed [DATA_WIDTH/2-1:0] max_diff_re, max_diff_im;

initial begin

max_diff_re = 0;

max_diff_im = 0;

rstn = 0;

#500

rstn = 1;

#SIM_TIME

sim_finish();

$stop();

end

task sim_finish;

begin

if(fp_testin!=0)

$fclose(fp_testin);

if(fp_matlab_out!=0)

$fclose(fp_matlab_out);

if(fp_sim_out)

$fclose(fp_sim_out);

if(fp_outdiff!=0)

$fclose(fp_outdiff);

end

endtask

initial

begin

fp_testin = 0;

fp_testin= $fopen("txt_file/input_data.txt","r");

if(fp_testin==0)

begin

$display("input_data.txt open failed!");

sim_finish();

$stop();

end

else begin

$fscanf(fp_testin, "%d, %d\n",matlab_in_re,matlab_in_im);

end

fp_matlab_out = 0;

fp_matlab_out = $fopen("txt_file/matlab_out.txt","r");

if(fp_matlab_out==0)

begin

$display("fp_matlab_out.txt open failed!");

sim_finish();

$stop();

end

else begin

$fscanf(fp_matlab_out,"%d, %d\n",matlab_out_re,matlab_out_im);

end

fp_sim_out = 0;

fp_sim_out = $fopen("txt_file/modelsim_out.txt","w");

if(fp_sim_out == 0)

begin

$display("modelsim_out_re.txt open failed!");

sim_finish();

$stop();

end

fp_outdiff = 0;

fp_outdiff = $fopen("text_file/outdiff.txt","w");

if(fp_outdiff==0)

begin

$display("outdiff.txt open failed!");

sim_finish();

$stop();

end

end

always @(posedge clk)

begin

if(stest_wvalid && stest_wready) //ready to change

begin

if(~$feof(fp_testin))

$fscanf(fp_testin, "%d, %d\n",matlab_in_re,matlab_in_im);

end

else

begin

matlab_in_re

matlab_in_im

end

end

always @(posedge clk_100)

begin

if(mfc_wready && mfc_wvalid)

begin

matlab_diff_re

matlab_diff_im

matlab_diff_re2

matlab_diff_im2

if(max_diff_re

begin

max_diff_re

$display("max_diff_re:%d max_diff_im:%d\n",max_diff_re,max_diff_im);

end

else if(max_diff_re

begin

max_diff_re

$display("max_diff_re:%d max_diff_im:%d\n",max_diff_re,max_diff_im);

end

if(max_diff_im

begin

max_diff_im

$display("max_diff_re:%d max_diff_im:%d\n",max_diff_re,max_diff_im);

end

else if(max_diff_im

begin

max_diff_im

$display("max_diff_re:%d max_diff_im:%d\n",max_diff_re,max_diff_im);

end

$fscanf(fp_matlab_out,"%d, %d\n",matlab_out_re,matlab_out_im);

$fwrite(fp_sim_out, "%d, %d\n", mfc_wdata_re,mfc_wdata_im);

$fwrite(fp_outdiff, "%d, %d\n",matlab_diff_re,matlab_diff_im);

end

end

endmodule