module test(

input [1:0] ina,

input [1:0] inb,

input in_sel,

input clk,

input clear,

output reg out_a,

output reg out_b

);

wire eq0,eq1,eq2,eq3;

wire [1:0] result;

wire d1;

wire d2;

assign result = (in_sel)?inb:ina;

assign {eq3,eq2,eq1,eq0} = (result == 2"b0) ?{3"b0,1"b1}

(result == 2"b1) ?{2"b0,1"b1,1"b0} :

(result == 2"b2) ?{1"b0,1"b1,2"b0}:

{1"b1,3"b0};

assign d1 = ~(eq0 | eq1);

assign d2 = ~(eq2|eq3);

always @(posedge clk or posedge clear)

begin

if(clear == 1"b1)

begin

out_1

out_2

end

else

begin

out_1

out_2

end

end

endmodule