設計原理 計數時鐘由模為60的秒計數器模組、模為60的分計數模組、模為24的小時計數器模組、指示燈與報警器的模組、分/小時設定模組及輸出顯示模組等組成。秒計數器模組的進位輸出為分計數器模組的進位輸入，分計數器模組的進位輸出為小時計數器模組的進位輸入。其中秒計數器模組中應有分鐘的設定，分計數器模組中應有小時的設定。 內容 設計一個計數時鐘，使其具有24小時計數功能。透過“多功能複用按鍵F1-F12”訊號接線組“F1_12(T)”的F9~F12的任意引線插孔可設定小時和分鐘的值，並具有整點報時的功能。 電路原理圖 模組說明：計數時鐘由60秒計數器模組XSECOND、60分計數器模組XMINUTE、24小時計數器模組XHOUR等六個模組構成。秒計數器模組的進位輸出為分計數器模組的進位輸入，分計數器模組中有小時的設定。透過SW1、SW2、SW3、SW4可設定小時和分鐘的值，並具有整點報時的功能。 輸入訊號：SETMIN為分鐘設定訊號；SETHOUR為小時設定訊號；RESET為全域性復位訊號；CLK為全域性時鐘訊號；CKDSP為數碼管動態掃描訊號。 輸出訊號：SPEAK為蜂鳴器報時訊號；LAMP[2..0]為指示燈訊號；A~G為數碼管七個段位訊號；SS[2..0]為數碼管段位譯碼控制訊號。 說明與電路連線 指示燈訊號LAMP2~LAMP0為獨立擴充套件下載板上CPLD器件的第11、10、9腳，內部已連線並已鎖定，無需外接連線。 蜂鳴器報時訊號SPEAK為獨立擴充套件下載板CPLD器件的第31腳，內部已連線並已鎖定，無需外接連線。 撥碼開關SW1~SW7內部已連線並已鎖定，無需外接連線。 數碼管七個段位訊號A~G為獨立擴充套件下載板上CPLD器件的第86、87、88、89、90、92、93腳，應接數碼管段位引線接線組KPL_AH，從左到右依次對應的A、B、C、D、E、F、G引線插孔。 數碼管段位譯碼控制訊號SS0、SS1、SS2為獨立擴充套件下載板上CPLD器件的第68、69、70腳，為數碼管的位選掃描訊號，分別接訊號接線組DS1-8A（T）的SS0、SS1、SS2引線插孔（即在電源引線插孔組GND孔處）。 復位訊號RESET為獨立擴充套件下載板上CPLD器件的第71腳，應接“多功能複用按鍵F1-F12”訊號接線組“F1_12(T)”的F9~F12的任意一個插孔。 小時設定訊號SETHOUR為獨立擴充套件下載板CPLD器件的第73腳，應接“多功能複用按鍵F1-F12”訊號接線組“F1_12(T)”的F9~F12的任意一個插孔。 分鐘設定訊號SETMIN為獨立擴充套件下載板上CPLD器件的第74腳，應接“多功能複用按鍵F1-F12”訊號接線組“F1_12(T)”的F9~F12的任意一個插孔。 時鐘訊號CLK為獨立擴充套件下載板上CPLD器件的183腳（即GCLK2），應接時鐘訊號接線組“CLOCK（T）”的“FRQ（21）”引線插孔。 數碼管動態掃描訊號CKDSP為獨立擴充套件下載板上CPLD器件的79腳（即GCLK1），應接時鐘訊號接線組“CLOCK（T）”的“FRQ（11）”引線插孔。 參考源程式 library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity xsecond is port ( clk: in STD_LOGIC; clkset: in STD_LOGIC; setmin: in STD_LOGIC; reset: in STD_LOGIC; secout: out STD_LOGIC_VECTOR (6 downto 0); enmin: out STD_LOGIC ); end xsecond; architecture xsecond_arch of xsecond is signal sec : std_logic_vector(6 downto 0); signal emin : std_logic; signal sec1 : std_logic; begin -- <<enter your statements here>> process(reset,sec,emin,setmin,clkset) begin if reset="0" then enmin<="0"; secout<="0000000"; sec1<="1"; else sec1<="0"; secout<=sec; if clkset="1" and clkset"event then if setmin="0" then enmin<="1"; else enmin<=emin; end if; end if; end if; end process; process(clk,sec1) alias lcount : std_logic_vector(3 downto 0) is sec(3 downto 0); alias hcount : std_logic_vector(2 downto 0) is sec(6 downto 4); begin if sec1="1" then sec<="0000000"; else if (clk="1" and clk"event) then if lcount=9 then lcount<="0000"; if hcount/=5 then hcount<=hcount+1; emin<="0"; else hcount<="000"; emin<="1"; end if; else lcount<=lcount+1; emin<="0"; end if; end if; end if; end process; end xsecond_arch; library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity xminute is port ( clkmin: in STD_LOGIC; reset: in STD_LOGIC; sethour: in STD_LOGIC; clk: in STD_LOGIC; minout: out STD_LOGIC_VECTOR (6 downto 0); enhour: out STD_LOGIC ); end xminute; architecture xminute_arch of xminute is signal min : std_logic_vector(6 downto 0); signal ehour : std_logic; signal min1 : std_logic; begin -- <<enter your statements here>> process(reset,clk,sethour,min,ehour) begin if reset="0" then enhour<="0"; minout<="0000000"; min1<="0"; else min1<="1"; minout<=min; if clk="1" and clk"event then if sethour="0" then enhour<="1"; else enhour<=ehour; end if; end if; end if; end process; process(clkmin,min1) alias lcountm : std_logic_vector(3 downto 0) is min(3 downto 0); alias hcountm : std_logic_vector(2 downto 0) is min(6 downto 4); begin if min1="0" then min<="0000000"; else if (clkmin="1" and clkmin"event) then if lcountm=9 then lcountm<="0000"; if hcountm/=5 then hcountm<=hcountm+1; ehour<="0"; else hcountm<="000"; ehour<="1"; end if; else lcountm<=lcountm+1; ehour<="0"; end if; end if; end if; end process; end xminute_arch; library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity xhour is port ( clkhour: in STD_LOGIC; reset: in STD_LOGIC; hourout: out STD_LOGIC_VECTOR (5 downto 0) ); end xhour; architecture xhour_arch of xhour is signal hour : std_logic_vector(5 downto 0); begin -- <<enter your statements here>> process(reset,clkhour,hour) alias lcount : std_logic_vector(3 downto 0) is hour(3 downto 0); alias hcount : std_logic_vector(1 downto 0) is hour(5 downto 4); begin if reset="0" then hourout<="000000"; hour<="000000"; else if (clkhour="1" and clkhour"event) then if lcount=9 then lcount<="0000"; hcount<=hcount+1; else if hour="100011" then hour<="000000"; else lcount<=lcount+1; end if; end if; end if; hourout<=hour; end if; end process; end xhour_arch; library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity xalert is port ( clk: in STD_LOGIC; d_in: in STD_LOGIC_VECTOR (6 downto 0); speak: out STD_LOGIC; d_out: out STD_LOGIC_VECTOR (2 downto 0) ); end xalert; architecture xalert_arch of xalert is type state is (s1,s2,s3,s4); signal next_state,current_state : state; begin -- <<enter your statements here>> process(clk,current_state,d_in) begin if d_in/="0000000" then speak<="0"; next_state<=s1; current_state<=s1; d_out<="000"; else if clk="1" and clk"event then speak<="1"; current_state<=next_state; end if; case current_state is when s1 => d_out<="000"; next_state<=s2; when s2 => d_out<="001"; next_state<=s3; when s3 => d_out<="010"; next_state<=s4; when s4 => d_out<="100"; next_state<=s1; when others => d_out<="000"; null; end case; end if; end process; end xalert_arch; library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity xsettime is port ( hour: in STD_LOGIC_VECTOR (5 downto 0); min: in STD_LOGIC_VECTOR (6 downto 0); sec: in STD_LOGIC_VECTOR (6 downto 0); reset: in STD_LOGIC; clk: in STD_LOGIC; sel: out STD_LOGIC_VECTOR (2 downto 0); d_out: out STD_LOGIC_VECTOR (3 downto 0) ); end xsettime; architecture xsettime_arch of xsettime is signal sel1 : std_logic_vector(2 downto 0); begin -- <<enter your statements here>> process(clk,reset,sel1,hour,min,sec) begin if reset="0" then sel<="000"; d_out<="0000"; sel1<="000"; else if (clk="1" and clk"event) then if sel1<5 then sel1<=sel1+1; else sel1<="000"; end if; end if; sel<=sel1; case sel1 is when "000" => d_out(3)<="0"; d_out(2)<="0"; d_out(1)<=hour(5); d_out(0)<=hour(4); when "001" => d_out<=hour(3 downto 0); when "010" => d_out(3)<="0"; d_out(2)<=min(6); d_out(1)<=min(5); d_out(0)<=min(4); when "011" => d_out<=min(3 downto 0); when "100" => d_out(3)<="0"; d_out(2)<=sec(6); d_out(1)<=sec(5); d_out(0)<=sec(4); when "101" => d_out<=sec(3 downto 0); when others => null; end case; end if; end process; end xsettime_arch; library IEEE; use IEEE.std_logic_1164.all; entity xdeled is port ( d_in: in STD_LOGIC_VECTOR (3 downto 0); a: out STD_LOGIC; b: out STD_LOGIC; c: out STD_LOGIC; d: out STD_LOGIC; e: out STD_LOGIC; f: out STD_LOGIC; g: out STD_LOGIC ); end xdeled; 才五分啊，太少了吧
設計原理 計數時鐘由模為60的秒計數器模組、模為60的分計數模組、模為24的小時計數器模組、指示燈與報警器的模組、分/小時設定模組及輸出顯示模組等組成。秒計數器模組的進位輸出為分計數器模組的進位輸入，分計數器模組的進位輸出為小時計數器模組的進位輸入。其中秒計數器模組中應有分鐘的設定，分計數器模組中應有小時的設定。 內容 設計一個計數時鐘，使其具有24小時計數功能。透過“多功能複用按鍵F1-F12”訊號接線組“F1_12(T)”的F9~F12的任意引線插孔可設定小時和分鐘的值，並具有整點報時的功能。 電路原理圖 模組說明：計數時鐘由60秒計數器模組XSECOND、60分計數器模組XMINUTE、24小時計數器模組XHOUR等六個模組構成。秒計數器模組的進位輸出為分計數器模組的進位輸入，分計數器模組中有小時的設定。透過SW1、SW2、SW3、SW4可設定小時和分鐘的值，並具有整點報時的功能。 輸入訊號：SETMIN為分鐘設定訊號；SETHOUR為小時設定訊號；RESET為全域性復位訊號；CLK為全域性時鐘訊號；CKDSP為數碼管動態掃描訊號。 輸出訊號：SPEAK為蜂鳴器報時訊號；LAMP[2..0]為指示燈訊號；A~G為數碼管七個段位訊號；SS[2..0]為數碼管段位譯碼控制訊號。 說明與電路連線 指示燈訊號LAMP2~LAMP0為獨立擴充套件下載板上CPLD器件的第11、10、9腳，內部已連線並已鎖定，無需外接連線。 蜂鳴器報時訊號SPEAK為獨立擴充套件下載板CPLD器件的第31腳，內部已連線並已鎖定，無需外接連線。 撥碼開關SW1~SW7內部已連線並已鎖定，無需外接連線。 數碼管七個段位訊號A~G為獨立擴充套件下載板上CPLD器件的第86、87、88、89、90、92、93腳，應接數碼管段位引線接線組KPL_AH，從左到右依次對應的A、B、C、D、E、F、G引線插孔。 數碼管段位譯碼控制訊號SS0、SS1、SS2為獨立擴充套件下載板上CPLD器件的第68、69、70腳，為數碼管的位選掃描訊號，分別接訊號接線組DS1-8A（T）的SS0、SS1、SS2引線插孔（即在電源引線插孔組GND孔處）。 復位訊號RESET為獨立擴充套件下載板上CPLD器件的第71腳，應接“多功能複用按鍵F1-F12”訊號接線組“F1_12(T)”的F9~F12的任意一個插孔。 小時設定訊號SETHOUR為獨立擴充套件下載板CPLD器件的第73腳，應接“多功能複用按鍵F1-F12”訊號接線組“F1_12(T)”的F9~F12的任意一個插孔。 分鐘設定訊號SETMIN為獨立擴充套件下載板上CPLD器件的第74腳，應接“多功能複用按鍵F1-F12”訊號接線組“F1_12(T)”的F9~F12的任意一個插孔。 時鐘訊號CLK為獨立擴充套件下載板上CPLD器件的183腳（即GCLK2），應接時鐘訊號接線組“CLOCK（T）”的“FRQ（21）”引線插孔。 數碼管動態掃描訊號CKDSP為獨立擴充套件下載板上CPLD器件的79腳（即GCLK1），應接時鐘訊號接線組“CLOCK（T）”的“FRQ（11）”引線插孔。 參考源程式 library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity xsecond is port ( clk: in STD_LOGIC; clkset: in STD_LOGIC; setmin: in STD_LOGIC; reset: in STD_LOGIC; secout: out STD_LOGIC_VECTOR (6 downto 0); enmin: out STD_LOGIC ); end xsecond; architecture xsecond_arch of xsecond is signal sec : std_logic_vector(6 downto 0); signal emin : std_logic; signal sec1 : std_logic; begin -- <<enter your statements here>> process(reset,sec,emin,setmin,clkset) begin if reset="0" then enmin<="0"; secout<="0000000"; sec1<="1"; else sec1<="0"; secout<=sec; if clkset="1" and clkset"event then if setmin="0" then enmin<="1"; else enmin<=emin; end if; end if; end if; end process; process(clk,sec1) alias lcount : std_logic_vector(3 downto 0) is sec(3 downto 0); alias hcount : std_logic_vector(2 downto 0) is sec(6 downto 4); begin if sec1="1" then sec<="0000000"; else if (clk="1" and clk"event) then if lcount=9 then lcount<="0000"; if hcount/=5 then hcount<=hcount+1; emin<="0"; else hcount<="000"; emin<="1"; end if; else lcount<=lcount+1; emin<="0"; end if; end if; end if; end process; end xsecond_arch; library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity xminute is port ( clkmin: in STD_LOGIC; reset: in STD_LOGIC; sethour: in STD_LOGIC; clk: in STD_LOGIC; minout: out STD_LOGIC_VECTOR (6 downto 0); enhour: out STD_LOGIC ); end xminute; architecture xminute_arch of xminute is signal min : std_logic_vector(6 downto 0); signal ehour : std_logic; signal min1 : std_logic; begin -- <<enter your statements here>> process(reset,clk,sethour,min,ehour) begin if reset="0" then enhour<="0"; minout<="0000000"; min1<="0"; else min1<="1"; minout<=min; if clk="1" and clk"event then if sethour="0" then enhour<="1"; else enhour<=ehour; end if; end if; end if; end process; process(clkmin,min1) alias lcountm : std_logic_vector(3 downto 0) is min(3 downto 0); alias hcountm : std_logic_vector(2 downto 0) is min(6 downto 4); begin if min1="0" then min<="0000000"; else if (clkmin="1" and clkmin"event) then if lcountm=9 then lcountm<="0000"; if hcountm/=5 then hcountm<=hcountm+1; ehour<="0"; else hcountm<="000"; ehour<="1"; end if; else lcountm<=lcountm+1; ehour<="0"; end if; end if; end if; end process; end xminute_arch; library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity xhour is port ( clkhour: in STD_LOGIC; reset: in STD_LOGIC; hourout: out STD_LOGIC_VECTOR (5 downto 0) ); end xhour; architecture xhour_arch of xhour is signal hour : std_logic_vector(5 downto 0); begin -- <<enter your statements here>> process(reset,clkhour,hour) alias lcount : std_logic_vector(3 downto 0) is hour(3 downto 0); alias hcount : std_logic_vector(1 downto 0) is hour(5 downto 4); begin if reset="0" then hourout<="000000"; hour<="000000"; else if (clkhour="1" and clkhour"event) then if lcount=9 then lcount<="0000"; hcount<=hcount+1; else if hour="100011" then hour<="000000"; else lcount<=lcount+1; end if; end if; end if; hourout<=hour; end if; end process; end xhour_arch; library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity xalert is port ( clk: in STD_LOGIC; d_in: in STD_LOGIC_VECTOR (6 downto 0); speak: out STD_LOGIC; d_out: out STD_LOGIC_VECTOR (2 downto 0) ); end xalert; architecture xalert_arch of xalert is type state is (s1,s2,s3,s4); signal next_state,current_state : state; begin -- <<enter your statements here>> process(clk,current_state,d_in) begin if d_in/="0000000" then speak<="0"; next_state<=s1; current_state<=s1; d_out<="000"; else if clk="1" and clk"event then speak<="1"; current_state<=next_state; end if; case current_state is when s1 => d_out<="000"; next_state<=s2; when s2 => d_out<="001"; next_state<=s3; when s3 => d_out<="010"; next_state<=s4; when s4 => d_out<="100"; next_state<=s1; when others => d_out<="000"; null; end case; end if; end process; end xalert_arch; library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity xsettime is port ( hour: in STD_LOGIC_VECTOR (5 downto 0); min: in STD_LOGIC_VECTOR (6 downto 0); sec: in STD_LOGIC_VECTOR (6 downto 0); reset: in STD_LOGIC; clk: in STD_LOGIC; sel: out STD_LOGIC_VECTOR (2 downto 0); d_out: out STD_LOGIC_VECTOR (3 downto 0) ); end xsettime; architecture xsettime_arch of xsettime is signal sel1 : std_logic_vector(2 downto 0); begin -- <<enter your statements here>> process(clk,reset,sel1,hour,min,sec) begin if reset="0" then sel<="000"; d_out<="0000"; sel1<="000"; else if (clk="1" and clk"event) then if sel1<5 then sel1<=sel1+1; else sel1<="000"; end if; end if; sel<=sel1; case sel1 is when "000" => d_out(3)<="0"; d_out(2)<="0"; d_out(1)<=hour(5); d_out(0)<=hour(4); when "001" => d_out<=hour(3 downto 0); when "010" => d_out(3)<="0"; d_out(2)<=min(6); d_out(1)<=min(5); d_out(0)<=min(4); when "011" => d_out<=min(3 downto 0); when "100" => d_out(3)<="0"; d_out(2)<=sec(6); d_out(1)<=sec(5); d_out(0)<=sec(4); when "101" => d_out<=sec(3 downto 0); when others => null; end case; end if; end process; end xsettime_arch; library IEEE; use IEEE.std_logic_1164.all; entity xdeled is port ( d_in: in STD_LOGIC_VECTOR (3 downto 0); a: out STD_LOGIC; b: out STD_LOGIC; c: out STD_LOGIC; d: out STD_LOGIC; e: out STD_LOGIC; f: out STD_LOGIC; g: out STD_LOGIC ); end xdeled; 才五分啊，太少了吧